Semiconductor structure and method for fabricating same

ABSTRACT

Embodiments relate to the field of semiconductors, and provide a semiconductor structure and a method for fabricating the same. The semiconductor structure includes a first wafer and a second wafer. A surface of the first wafer has a first electrode plate, a first dielectric layer and a first dummy pad stacked in sequence to constitute a capacitor; and the surface of the first wafer further has a first functional pad, and the first functional pad and the first dummy pad are arranged on a same layer. The second wafer is bonded to the first wafer, and a surface of the second wafer has a second dummy pad and a second functional pad arranged on a same layer. The first dummy pad is bonded to the second dummy pad, and the first functional pad is bonded to the second functional pad.

CROSS REFERENCE

This application is a continuation of PCT/CN2022/107694, filed on Jul.25, 2022, which claims priority to Chinese Patent Application No.202210804053.3 titled “SEMICONDUCTOR STRUCTURE AND METHOD FORFABRICATING SAME” and filed on Jul. 7, 2022, the entire contents ofwhich are incorporated herein by reference.

TECHNICAL FIELD

Embodiments of the present disclosure relate to the field ofsemiconductors, and more particularly, to a semiconductor structure anda method for fabricating the same.

BACKGROUND

Hybrid Bonding is a technology that allows pads of two wafers todirectly contact to produce molecular bonding. The Hybrid Bonding canprovide higher interconnection density, smaller and simpler circuits,larger bandwidth, and lower power consumption, so it is widely used inthe field of chip packaging.

However, space utilization of wafers using the Hybrid Bonding is nothigh.

SUMMARY

Embodiments of the present disclosure provide a semiconductor structureand a method for fabricating the same, which are at least beneficial toimproving space utilization of a wafer.

According to some embodiments of the present disclosure, one aspect ofthe embodiments of the present disclosure provides a semiconductorstructure. The semiconductor structure includes a first wafer and asecond wafer. A surface of the first wafer has a first electrode plate,a first dielectric layer and a first dummy pad stacked in sequence toconstitute a capacitor; and the surface of the first wafer further has afirst functional pad, and the first functional pad and the first dummypad are arranged on a same layer. The second wafer is bonded to thefirst wafer, and a surface of the second wafer has a second dummy padand a second functional pad arranged on a same layer. The first dummypad is bonded to the second dummy pad, and the first functional pad isbonded to the second functional pad.

According to some embodiments of the present disclosure, another aspectof the embodiments of the present disclosure further provides a methodfor fabricating the semiconductor structure. The method includes:providing a first wafer; forming, on a surface of the first wafer, afirst electrode plate, a first dielectric layer and a first dummy padstacked in sequence to constitute a capacitor; and forming a firstfunctional pad on the surface of the first wafer, where the firstfunctional pad and the first dummy pad are arranged on a same layer;providing a second wafer; forming, on a surface of the second wafer, asecond dummy pad and a second functional pad arranged on a same layer;and bonding the first dummy pad to the second dummy pad, and bonding thefirst functional pad to the second functional pad, such that the firstwafer is bonded to the second wafer.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings herein are incorporated in and constitute apart of this specification, illustrate embodiments conforming to thepresent disclosure and, together with the specification, serve toexplain the principles of the present disclosure. Apparently, theaccompanying drawings in the following description show merely someembodiments of the present disclosure, and persons of ordinary skill inthe art may still derive other drawings from these accompanying drawingswithout creative efforts.

FIG. 1 illustrates a sectional view of a semiconductor structure;

FIGS. 2 to 5 illustrate different sectional views of the semiconductorstructure provided by an embodiment of the present disclosure along astacking direction of a first wafer and a second wafer;

FIGS. 6 to 13 illustrate different sectional views of the semiconductorstructure provided by an embodiment of the present disclosure along adirection parallel to an upper surface of the first wafer;

FIG. 14 illustrates a partial sectional view of the semiconductorstructure provided by an embodiment of the present disclosure along thestacking direction of the first wafer and the second wafer; and

FIGS. 15 to 19 illustrate schematic structural diagrams corresponding tosteps of a method for fabricating the semiconductor structure providedby an embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Referring to FIG. 1 , it is found through analysis that in a hybridbonding process of a first wafer 100 and a second wafer 200, a surfacedielectric layer 300 is polished by means of chemical mechanicalpolishing process. However, because a distance between functional pads120 is larger, recesses may be generated on the surface dielectric layer300. Therefore, number of pads may be increased to ensure that thedielectric layer after the chemical mechanical polishing has a smoothsurface. The increased pads are called dummy pads 110, which do not haveany other functions, so space on a surface of the wafer cannot be fullyutilized.

Embodiments of the present disclosure provide a semiconductor structure,which includes a first wafer and a second wafer bonded to each other. Asurface of the first wafer has a first electrode plate and a firstdielectric layer, where the first electrode plate and the firstdielectric layer constitute a capacitor together with a first dummy padof the first wafer. The capacitor may replace component capacitors inthe first wafer and the second wafer, thereby improving spaceutilization of the wafer.

The embodiments of the present disclosure will be described in detailbelow in conjunction with the accompanying drawings. However, a personof ordinary skill in the art may understand that in the embodiments ofthe present disclosure, many technical details are put forward such thata reader may better understand the present disclosure. However, thetechnical solutions requested to be protected by the embodiments of thepresent disclosure may also be implemented even without these technicaldetails or various variations and modifications based on the followingembodiments.

As shown in FIG. 2 to FIG. 14 , an embodiment of the present disclosureprovides a semiconductor structure, which includes a first wafer 1 and asecond wafer 2. A surface of the first wafer 1 has a first electrodeplate 17, a first dielectric layer 16 and a first dummy pad 11 stackedin sequence to constitute a capacitor C; and the surface of the firstwafer 1 further has a first functional pad 12, and the first functionalpad 12 and the first dummy pad 11 are arranged on a same layer. Thesecond wafer 2 is bonded to the first wafer 1, and a surface of thesecond wafer 2 has a second dummy pad 21 and a second functional pad 22arranged on a same layer. The first dummy pad 11 is bonded to the seconddummy pad 21, and the first functional pad 12 is bonded to the secondfunctional pad 22. That is, the capacitor C is formed by making full useof the dummy pads in a hybrid bonding wafer, to realize capacitanceexpansion and improve the space utilization of the wafer.

The semiconductor structure will be described in detail below withreference to the accompanying drawings.

First of all, it is to be noted that the semiconductor structure may bea chip, such as a memory chip. For example, the memory chip may be adynamic random access memory (DRAM).

Referring to FIGS. 2 to 5 , a material of the first wafer 1 and amaterial of the second wafer 2 may be silicon or germanium. The firstwafer 1 and the second wafer 2 may have structures such as transistors,element capacitors, word lines, and bit lines, etc. The first wafer 1and the second wafer 2 may have different structures. For example, oneof the first wafer 1 and the second wafer 2 has the transistors, and theother one has the element capacitors. In addition, elements in the firstwafer 1 and elements in the second wafer 2 may also be the same. Forexample, both of the first wafer 1 and the second wafer 2 have thetransistors and the element capacitors.

The first dummy pad 11, the first functional pad 12, the second dummypad 21 and the second functional pad 22 may have same material such asmetal, which may be, for example, copper, gold, or aluminum, etc. Amaterial of the first dielectric layer 16 may be Si₃N₄, SiO₂, SiCN, HfO,or ZrO, etc. A material of the first electrode plate 17 may be the sameas that of the pad. For example, both the material of the firstelectrode plate 17 and the material of the pad are copper.

The first electrode plate 17 is positioned on the surface of the firstwafer 1, which mainly includes following two cases. The surface of thefirst wafer 1 is a plane, and the first electrode plate 17 is directlyformed on the surface of the first wafer 1; or the surface of the firstwafer 1 is further provided with a groove 5 (referring to FIG. 16 ), andthe first electrode plate 17 is positioned in the groove 5. In addition,the first dielectric layer 16 is positioned on the surface of the firstwafer 1, which mainly in includes following two cases. The surface ofthe first wafer 1 the plane, and the first dielectric layer 16 isdirectly formed on the surface of the first wafer 1; or as shown inFIGS. 2 to 5 , the surface of the first wafer 1 is provided with thegroove 5, and the first dielectric layer 16 is positioned in the groove5.

It is to be noted that the capacitor C constituted of the first dummypad 11, the first dielectric layer 16 and the first electrode plate 17may expand capacitances of the element capacitors or replace the elementcapacitors, such that it is advantageous to improving performance of thesemiconductor structure, and improving the space utilization of thesurface of the wafer. In some other embodiments, the capacitor C mayalso be used as a passive device in a circuit other than the first wafer1 and the second wafer 2. Because the capacitor C is packaged with thefirst wafer 1 and the second wafer 2, this is advantageous to improvingintegration of package.

An area of the pad and an area of the first electrode plate 17 will bedescribed below. It is worth noting that the area refers to an area ofan orthographic projection of the pad and the first electrode plate 17on an upper surface of the first wafer 1.

In some embodiments, referring to FIG. 2 and FIGS. 4 to 5 , the area ofthe first electrode plate 17 is equal to that of the first dummy pad 11,which is beneficial to simplify fabrication processes. In some otherembodiments, referring to FIG. 3 , the area of the first electrode plate17 is greater than that of the first dummy pad 11. It is to be notedthat setting an area difference between the first electrode plate 17 andthe first dummy pad 11 is beneficial to provide a certain margin for analignment error, to increase an orthographic projection area for thefirst electrode plate 17 and the first dummy pad 11. In addition, whenthe area of the first dummy pad 11 is smaller, this can prevent thefirst dummy pad 11 from occupying too much space of a first surfacedielectric layer 3, thereby improving an effect of isolation between thefirst dummy pad 11 and the first functional pad 12.

In some embodiments, referring to FIG. 2 and FIGS. 4 to 5 , the area ofthe first dummy pad 11 is equal to that of the second dummy pad 21,which is beneficial to simplify the fabrication processes. In some otherembodiments, referring to FIG. 3 , the area of the first dummy pad 11 isgreater than that of the second dummy pad 21. It is to be noted thatsetting an area difference between the first dummy pad 11 and the seconddummy pad 21 is beneficial to provide a certain margin for the alignmenterror, to avoid occurrence of erroneously bonding the first dummy pad 11to the non-corresponding second dummy pad 21 or the second functionalpad 22. That is, when the area of the first dummy pad 11 is equal tothat of the second dummy pad 21, the first dummy pad 11 likely may beelectrically connected to other pads next to the second dummy pad 21corresponding to the first dummy pad 11 in the event of the alignmenterror.

In some embodiments, referring to FIGS. 2 to 5 , the area of the firstdummy pad 11 is equal to that of the first functional pad 12, and thearea of the second dummy pad 21 is equal to that of the secondfunctional pad 22. Therefore, the fabrication processes are simpler, andthe semiconductor structure has better uniformity.

For example, the area of the first dummy pad 11 ranges from 0.01 um² to100 um², such as 1 um², 50 um² or 80 um². The area of the second dummypad 21 ranges from 0.01 um² to 100 um², such as 3 um², 20 um² or 60 um².The area of the first functional pad 12 ranges from 0.01 um² to 100 um²,such as 7 um², 40 um² or 90 um². The area of the second functional pad22 ranges from 0.01 um² to 100 um², such as 8 um², 35 um² or 78 um².When the area of the first dummy pad 11, the area of the second dummypad 21, the area of the first functional pad 12 and the area of thesecond functional pad 22 are within the above range, it is beneficial toimprove a bonding strength, which can provide more sufficient space tothe first surface dielectric layer 3 and a second surface dielectriclayer 4, to ensure a better effect of isolation between the pads.

Referring to FIGS. 2 to 5 , the first wafer 1 has a first wiring layer15 therein, and the second wafer 2 has a second wiring layer 25 therein.The first wiring layer 15 and the second wiring layer 25 guide thestructures in the first wafer 1 and the structures in the second wafer 2out respectively for rewiring, to facilitate bonding during packaging.

Referring to FIGS. 2 to 5 , the first wafer 1 has a first conductiveplug 13 therein, where the first conductive plug 13 is positionedbetween the first electrode plate 17 and the first wiring layer 15, andis connected to both the first electrode plate 17 and the first wiringlayer 15. That is, the first electrode plate 17 may be electricallyconnected to the first wiring layer 15 through the first conductive plug13. The second wafer 2 has a third conductive plug 23 positioned betweenthe second wiring layer 25 and the second dummy pad 21, and the thirdconductive plug 23 is connected to the second wiring layer 25 and thesecond dummy pads 21. That is, the second dummy pad 21 may beelectrically connected to the second wiring layer 25 through the thirdconductive plug 23. Because the second dummy pad 21 is bonded to thefirst dummy pad 11, the second dummy pad 21 and the first dummy pad 11may be entirely regarded as other electrode plate of the capacitor C.The two electrode plates of the capacitor C are electrically conductivethrough the first wiring layer 15 and the second wiring layer 25,respectively. Because the first wiring layer 15 and the second wiringlayer 25 are positioned on two wafers, the capacitor C may beinterpreted as an across-wafer capacitor C.

In some other embodiments, the capacitor C may not be connected to thesecond wiring layer 25. That is, the second dummy pad 21 or the firstdummy pad 11 may also be electrically connected to an external componentother than the first wafer 1 and the second wafer 2 through a connectingstructure such as a wire, to connect the capacitor C to an circuit inthe external component. Similarly, the capacitor C also may not beconnected to the first wiring layer 15. That is, the capacitor C may beconnected to one of the first wiring layer 15 and the second wiringlayer 25.

Referring to FIGS. 2 to 5 , the first wafer 1 further has a secondconductive plug 14 therein, where the second conductive plug 14 ispositioned between the first wiring layer 15 and the first functionalpad 12, and is connected to both the first wiring layer 15 and the firstfunctional pad 12. That is, the first functional pad 12 may beelectrically connected to structures such as the transistors in thefirst wafer 1 through the second conductive plug 14 and the first wiringlayer 15. The second wafer 2 also has a fourth conductive plug 24therein, where the fourth conductive plug 24 is positioned between thesecond wiring layer 25 and the second functional pad 22, and isconnected to both the second wiring layer 25 and the second functionalpad 22. That is, the second functional pad 22 may be electricallyconnected to structures such as the transistors in the second wafer 2through the fourth conductive plug 24 and the second wiring layer 25.Because the first functional pad 12 is bonded to the second functionalpad 22, the electrical connection of the structures in the first wafer 1and the second wafer 2 is achieved.

The capacitor C will be described in detail below.

Referring to FIGS. 2 to 5 , the capacitor C constituted of the firstdummy pad 11, the first dielectric layer 16 and the first electrodeplate 17 is called a first capacitor C1. In some other embodiments,referring to FIG. 5 , the surface of the second wafer 2 may further havea second electrode plate 27, a second dielectric layer 26 and a seconddummy pad 21 stacked to constitute a capacitor C, which is referred toas a second capacitor C2. The second electrode plate 27 is similar tothe first electrode plate 17, and the second dielectric layer 26 issimilar to the first dielectric layer 16. Reference may be made to thefirst electrode plate 27 and the first dielectric layer 16 for detaileddescription of the second electrode plate 27 and the second dielectriclayer 26.

Referring to FIGS. 2 to 3 , there may be one capacitor C. In someembodiments, the capacitor C may be either the first capacitor C1 or thesecond capacitor C2. Accordingly, the semiconductor structure may haveonly one first dummy pad 11 or second dummy pad 21. In some embodiments,the semiconductor structure may have a plurality of first dummy pads 11or a plurality of second dummy pads 21, except for dummy pads configuredto constitute the capacitor C, other dummy pads are only configured forbonding.

Referring to FIGS. 4 to 5 , there may be a plurality of capacitors C. Insome embodiments, referring to FIG. 4 , the plurality of capacitors Cmay be the first capacitors C1, or the plurality of capacitors C may bethe second capacitors C2; or, referring to FIG. 5 , some of thecapacitors C are the first capacitors C1, and some of the capacitors Care the second capacitors C2.

Hereinafter, a connection relationship between the plurality ofcapacitors C will be described in detail below by taking an examplewhere the capacitors C are the first capacitors C1.

In some embodiments, the plurality of capacitors C may be independent ofeach other.

That is, referring to FIGS. 4 to 5 , although the plurality ofcapacitors C are connected to the first wiring layer 15 and the secondwiring layer 25, the first wiring layer 15 includes a plurality of firstconductive parts 151 insulated from each other, and the second wiringlayer 25 includes a plurality of second conductive parts 251 insulatedfrom each other. The plurality of capacitors C are connected todifferent first conductive parts 151 through a plurality of firstconductive plugs 13, and the plurality of capacitors C are connected todifferent second conductive parts 251 through a plurality of thirdconductive plugs 23. Therefore, the first dummy pads 11 of the pluralityof capacitors C are still insulated from each other, and the firstelectrode plates 17 of the plurality of capacitors C are still insulatedfrom each other.

In some other embodiments, the plurality of capacitors C may also beconnected in parallel with each other. That is, the semiconductorstructure includes at least one capacitor bank C0, and the samecapacitor bank C0 includes a plurality of capacitors C connected inparallel. Referring to FIGS. 6 to 13 , parallel connection modes andarrangement modes of the capacitors C will be exemplified below.

First of all, it is to be noted that FIGS. 6 to 13 are sectional views,and FIGS. 6 to 7 are different sectional views of the same semiconductorstructure, where FIG. 6 shows a cross section of the first dummy pad 11and a cross section of the first functional pad 12, and FIG. 7 shows across section of the first wiring layer 15. FIGS. 8 to 9 are differentsectional views of the same semiconductor structure, where FIG. 8 showsa cross section of the first dummy pad 11 and a cross section of thefirst functional pads 12, and FIG. 9 shows the first wiring layer 15.FIGS. 10 to 11 show different sectional views of the same semiconductorstructure, where FIG. 10 shows the cross section of the first dummy pad11 and the cross section of the first functional pad 12, and FIG. 11shows the cross section of the first wiring layer 15. FIGS. 12 to 13show different sectional views of the same semiconductor structure,where FIG. 12 shows a cross section of the first electrode plate 17, andFIG. 13 shows the cross section of the first wiring layer 15.

In Example I, referring to FIGS. 6 to 11 , there are a plurality offirst electrode plates 17 and a plurality of first dummy pads 11, andthe plurality of first electrode plates 17 are arranged in one-to-onecorrespondence to the plurality of first dummy pads 11. Thesemiconductor structure further includes a third conductive part 153 anda fourth conductive part (not shown in the figure). The third conductivepart 153 is connected to the plurality of first conductive parts 151,such that the first electrode plates 17 of the plurality of capacitors Care electrically connected. The fourth conductive part is connected tothe plurality of second conductive parts 251, such that the first dummypads 11 of the plurality of capacitors C are connected to each other. Inthis way, a parallel connection of the plurality of capacitors C may beachieved. It is to be noted that the third conductive part 153 maybelong to the first wiring layer 15 or other wiring layers; and thefourth conductive part may belong to the second wiring layer 25 or otherwiring layers.

In some embodiments, referring to FIG. 6 , the semiconductor structurehas one capacitor bank C0, and the plurality of first dummy pads 11 ofthe plurality of capacitors C in the same capacitor bank C0 surround oneor more first functional pads 12. Correspondingly, referring to FIG. 7 ,the first conductive parts 151 electrically connected to the first dummypads 11 are connected to the third conductive part 153 to form anannular structure, which surrounds the first conductive parts 151electrically connected to the first functional pads 12. Correspondingly,the plurality of second dummy pads 21 of the plurality of capacitors Cin the same capacitor group C0 surround one or more second functionalpads 22. In this way, it is advantageous to improving uniformity ofdistribution of the pads, and shortening a length of the thirdconductive part 153.

In some other embodiments, referring to FIG. 8 , the semiconductorstructure has a plurality of capacitor banks C0, and the plurality offirst dummy pads 11 of the plurality of capacitors C in the samecapacitor bank C0 surround one or more first functional pads 12. Numberof the first functional pads 12 surrounded by different capacitor groupsC0 may be equal or may be not equal. Correspondingly, referring to FIG.9 , the first conductive parts 151 electrically connected to the firstdummy pads 11 are connected to the third conductive part 153 to form aplurality of annular structures, where each of the annular structuressurrounds the first conductive parts 151 electrically connected to thefirst functional pads 12. Correspondingly, the plurality of second dummypads 21 in the same capacitor group C0 surround one or more secondfunctional pads 22 correspondingly.

In some other embodiments, referring to FIG. 10 , there are a pluralityof capacitor banks C0, and the plurality of capacitors C in the samecapacitor bank C0 are arranged in the same direction. Correspondingly,the plurality of first dummy pads 11 in the same capacitor group C0 arearranged in the same direction. The plurality of second dummy pads 21 inthe same capacitor group C0 are arranged in the same direction.Correspondingly, referring to FIG. 11 , the plurality of firstconductive parts 151 in the same capacitor group C0 are arranged in thesame direction, such that the length of the third conductive part 153 isreduced. Similarly, the plurality of second conductive parts 251 in thesame capacitor group C0 may also be arranged in the same direction,which is beneficial to reduce a length of the fourth conductive part(not shown in the figure), to reduce resistance, and to improve signalquality.

With continued reference to FIGS. 10 to 11 , the plurality of capacitorbanks C0 are arranged in parallel, and both the first functional pad 12and the second functional pad 22 are positioned between adjacentcapacitor banks C0. In this way, it is beneficial to improve theuniformity of the distribution of the first functional pads 12, thefirst dummy pads 11, the second functional pads 22 and the second dummypads 21, thereby improving firmness of bonding and facilitating wiringlayout the first wiring layer 15 and the second wiring layer 25.

In Example 2, referring to FIG. 12 , there is one first electrode plate17 and a plurality of first dummy pads 11, and the plurality of firstdummy pads 11 are arranged opposite to the one first electrode plate 17.That is, the plurality of capacitors C share the one first electrodeplate 17. Therefore, there is no need to connect the plurality of firstconductive parts 151 through the third conductive parts 153, such thatthe first electrode plates 17 of the capacitors C are electricallyconnected to each other. In this way, the fabrication processes can besimplified and fabrication costs can be saved. In addition, theplurality of capacitors C may also share one first conductive plug 13and one first conductive part 151. That is, the first electrode plate 17shared by the plurality of capacitors C is connected to one firstconductive part 151 of the first wiring layer 15 through one firstconductive plug 13.

It is to be noted that the semiconductor structure further includes afourth conductive part (not shown in the figure), where the fourthconductive part may be connected to the plurality of second conductiveparts 251, such that the first dummy pads 11 of the plurality ofcapacitors C are conducted to each other. In this way, a parallelconnection of the plurality of capacitors C may be achieved.

It is worth noting that, in some embodiments, the capacitor C is onlyconstituted of the first dielectric layer 16, the first electrode plate17, and the first dummy pad 11. In some other embodiments, referring toFIG. 14 , the surface of the first wafer 1 further has a firstconnection layer 18; and the surface of the second wafer 2 further has asecond electrode plate 27, a second dielectric layer 26, and a secondconnection layer 28. To increase a surface area of the electrode plate,the capacitor C may also be constituted of the first electrode plate 17,the second electrode plate 27, the first connection layer 18, the secondconnection layer 28, the first dummy pad 11, the second dummy pad 21,the first dielectric layer 16, and the second dielectric layer 26. Forease of understanding, this capacitor C is referred to as a thirdcapacitor C3.

In some embodiments, referring to FIG. 14 , the second electrode plate27, the second dielectric layer 26 and the second dummy pad 21 aresequentially stacked on the surface of the second wafer 2. The secondconnection layer 28 is connected to the second electrode plate 27, andis spaced apart from the second dummy pad 21. The first connection layer18 is also connected to the first electrode plate 17 and is spaced apartfrom the first dummy pad 11. The first connection layer 18 is connectedto the second connection layer 28, and both the first connection layer18 and the second connection layer 28 extend in a directionperpendicular to the upper surface of the first wafer 1. That is, thefirst connection layer 18 and the second connection layer 28electrically connect the first electrode plate 17 to the secondelectrode plate 27. The first electrode plate 17, the second electrodeplate 27, the first connection layer 18 and the second connection layer28 have the same potential, and together act as one electrode plate ofthe third capacitor C3. The first dummy pad 11 is bonded to the seconddummy pad 21, to together serve as other electrode plate of the thirdcapacitor C3. The first dielectric layer 16, the second dielectric layer26, the first surface dielectric layer 3 between the first connectionlayer 18 and the first dummy pad 11, and the second surface dielectriclayer 4 between the second connection layer 28 and the second dummy pad21 together serve as the dielectric layer of the third capacitor C3. Inthis way, the orthographic projection area between the two electrodeplates of the third capacitor C3 is larger, thereby increasing thecapacitance of the capacitor.

With continued reference to FIG. 14 , in some embodiments, the firstelectrode plate 17 may be connected to the first wiring layer 15 throughthe first conductive plug 13; and the second dummy pad 21 may beelectrically connected to the second wiring layer 25 through the thirdconductive plug 23. That is, the two electrode plates of the thirdcapacitor C3 are electrically conductive through the first wiring layer15 and the second wiring layer 25. To provide a space for the thirdconductive plug 23, a width of the second electrode plate 27 may beappropriately reduced.

In some other embodiments, the second electrode plate 27 may beconnected to the second wiring layer 25 through the third conductiveplug 23, and the first dummy pad 11 may be electrically connected to thefirst wiring layer 15 through the first conductive plug 13. In someembodiments, the electrode plate constituted of the second dummy pads 21and the first dummy pads 11 may not be electrically connected to thefirst wiring layer 15 or the second wiring layer 25, but may beconnected to the circuit of the external component through a connectionstructure such as a wire.

To sum up, in the semiconductor structure provided by the embodiments ofthe present disclosure, the first electrode plate 17 and the firstdielectric layer 16 are additionally provided. The first electrode plate17 and the first dielectric layer 16 constitute, together with the firstdummy pad 11, the capacitor C, which may replace element capacitors in achip, thereby reducing an overall size of the chip while maintainingperformance of the chip. The increased capacitor C may be freely used bythe first wafer 1 and the second wafer 2. In addition, the plurality ofcapacitors C may be connected in parallel to expand the capacitance ofthe capacitor. In addition, the plurality of capacitors C may beconnected in parallel to form an annular structure, and may also formmultiple independent arrays respectively.

As shown in FIGS. 15 to 19 , another embodiment of the presentdisclosure provides a method for fabricating a semiconductor structure,where the method may be configured for fabricating the semiconductorstructure provided in the foregoing embodiments, and reference may bemade to the foregoing embodiments for the detailed description of thesemiconductor structure. It is to be noted that to facilitate thedescription and clearly illustrate the steps of the method forfabricating the semiconductor structure, FIGS. 15 to 19 are all partialschematic structural diagrams of the semiconductor structure.

The method for fabricating the semiconductor structure provided by yetanother embodiment of the present disclosure will be described in detailbelow with reference to the accompanying drawings.

Referring to FIG. 15 , the first wafer 1 is provided; the first wiringlayer 15 is formed in the first wafer 1; and a first conductive plug 13and a second conductive plug 14 connected to the first wiring layer 15are formed in the first wafer 1.

In some embodiments, a metal layer is deposited on the entire surface toserve as an initial first wiring layer, and the initial first wiringlayer is patterned to form a plurality of mutually insulated firstconductive parts 151 to constitute the first wiring layer 15. The firstwafer 1 is etched to form vias exposing the first wiring layer 15, andmetal is deposited in the vias to form the first conductive plug 13 andthe second conductive plug 14.

Referring to FIG. 16 , the first wafer 1 is removed by a part ofthickness to form a groove 5 in the first wafer 1, where the groove 5 ispositioned directly above the first conductive plug 13. For example, thegroove 5 is formed by means of a dry etching process. During theformation of the groove 5, the first conductive plug 13 is also removedby a part of length.

Referring to FIG. 17 , the first electrode plate 17 is formed in thegroove 5, and the first electrode plate 17 is connected to the firstconductive plug 13. For example, a metal layer is deposited in thegroove 5, and the metal layer is etched back, and a remaining part ofthe metal layer is used as the first electrode plate 17.

With continued reference to FIG. 17 , the first dielectric layer 16 isformed in the groove, and the first dielectric layer 16 also covers thefirst electrode plate 17. For example, an insulating material isdeposited in the groove 5 by means of a chemical vapor depositionprocess to form the first dielectric layer 16.

Referring to FIG. 18 , the first surface dielectric layer 3 is formed onthe surface of the first wafer 1. For example, the insulating materialis deposited on the surface of the first wafer 1 by means of thechemical vapor deposition process to form the first surface dielectriclayer 3. In some embodiments, the first dielectric layer 16 and thefirst surface dielectric layer 3 may be formed in the same step, whichis beneficial to simplify the fabrication processes.

With continued reference to FIG. 18 , the first dummy pad 11 and thefirst functional pad 12 are formed in the first surface dielectric layer3, where the first dummy pad 11 is positioned directly above the firstelectrode plate 17, and the first functional pad 12 is connected to thesecond conductive plug 14. For example, the first surface dielectriclayer 3 is patterned to form a plurality of filling grooves, and themetal layer is deposited in the plurality of filling grooves to serve asthe first dummy pad 11 and the first functional pad 12.

So far, based on FIGS. 15 to 18 , the first electrode plate 17, thefirst dielectric layer 16 and the first dummy pad 11 stacked in sequencemay be formed on the surface of the first wafer 1, to constitute thecapacitor C. In addition, the first functional pad 12 may also be formedon the surface of the first wafer 1, where the first functional pad 12and the first dummy pad 11 are arranged on the same layer.

Referring to FIG. 19 , the second wafer 2 is provided; and the seconddummy pad 21 and the second functional pad 22, which are arranged on thesame layer, are formed on the surface of the second wafer 2. The thirdconductive plug 23, the fourth conductive plug 24 and the second wiringlayer 25 may also be formed in the second wafer 2. Reference may be madeto the first wafer 1 for a detailed description of the second wafer 2,which is not to be described in detail here.

With continued reference to FIG. 19 , the first dummy pad 11 is bondedto the second dummy pad 21, and the first functional pad 12 is bonded tothe second functional pad 22, such that the first wafer 1 is bonded tothe second wafer 2. Under the action of a high temperature and apressure, the first wafer 1 and the second wafer 2 are bonded togetherby Van der Waals force, molecular force, and atomic force. It is to benoted that a bonding manner between the first wafer 1 and the secondwafer 2 may be as below: front surfaces of the first wafer 1 and thesecond wafer 2 are bonded together; or, the front surface of one of thefirst wafer 1 and the second wafer 2 is bonded to a back surface of theother one.

To sum up, in the embodiments of the present disclosure, before formingthe first dummy pad 11, the first electrode plate 17 and the firstdielectric layer 16 are formed in the first wafer 1, thereby thecapacitor C is formed. The capacitor C may replace the element capacitorin the first wafer 1 or the second wafer 2, or may be configured toincrease the capacitance of the element capacitor. In this way, thespace utilization of the surface of wafer can be improved.

In the description of this specification, reference to the descriptionof the terms “some embodiments”, “for example”, etc. means that aparticular feature, structure, material or characteristic described inconnection with this embodiment or example is included in at least oneembodiment or example of the present disclosure. The schematicrepresentation of the above terms throughout this specification are notnecessarily referring to the same embodiment or example. Furthermore,the features, structures, materials, or characteristics described may becombined in any suitable manner in one or more embodiments or examples.In addition, without contradiction, those skilled in the art may combinedifferent embodiments or examples described in the specification andfeatures of different embodiments or examples.

Although the embodiments of the present disclosure have been shown anddescribed above, it is to be understood that the above-mentionedembodiments are exemplary and should not be construed as limiting thepresent disclosure. Those of ordinary skill in the art may make changes,modifications, replacements and variations to the above embodimentswithout departing from the scope of the present disclosure. Therefore,all changes or embellishments made according to the claims and thespecification of the present disclosure shall still fall within thescope covered by the patent of the present disclosure.

What is claimed is:
 1. A semiconductor structure, comprising: a firstwafer, a surface of the first wafer having a first electrode plate, afirst dielectric layer and a first dummy pad stacked in sequence toconstitute a capacitor; and the surface of the first wafer furtherhaving a first functional pad, and the first functional pad and thefirst dummy pad being arranged on a same layer; and a second waferbonded to the first wafer, a surface of the second wafer having a seconddummy pad and a second functional pad arranged on a same layer; thefirst dummy pad being bonded to the second dummy pad, and the firstfunctional pad being bonded to the second functional pad.
 2. Thesemiconductor structure according to claim 1, wherein the first wafer isinternally provided with a first wiring layer, a first conductive plugand a second conductive plug, the first conductive plug being positionedbetween the first electrode plate and the first wiring layer and beingconnected to the first electrode plate and the first wiring layer, andthe second conductive plug being positioned between the first wiringlayer and the first functional pad and being connected to the firstwiring layer and the first functional pad; and wherein the second waferis internally provided with a second wiring layer, a third conductiveplug and a fourth conductive plug, the third conductive plug beingpositioned between the second wiring layer and the second dummy pad andbeing connected to the second wiring layer and the second dummy pad, andthe fourth conductive plug being positioned between the second wiringlayer and the second functional pad and being connected to the secondwiring layer and the second functional pad.
 3. The semiconductorstructure according to claim 2, wherein the semiconductor structurecomprises at least one capacitor bank, the same capacitor bankcomprising a plurality of capacitors in parallel.
 4. The semiconductorstructure according to claim 3, wherein there are a plurality of firstelectrode plates and a plurality of first dummy pads, and the pluralityof first electrode plates are arranged in one-to-one correspondence tothe plurality of first dummy pads.
 5. The semiconductor structureaccording to claim 3, wherein there is one first electrode plate and aplurality of first dummy pads, and the plurality of first dummy pads arearranged opposite to the one first electrode plate.
 6. The semiconductorstructure according to claim 3, wherein the plurality of first dummypads of the plurality of capacitors in the same capacitor bank surroundone or more of the first functional pads; and the plurality of seconddummy pads of the plurality of capacitors in the same capacitor banksurround one or more of the second functional pads.
 7. The semiconductorstructure according to claim 3, wherein there are a plurality ofcapacitor banks, and the plurality of capacitors in the same capacitorbank are arranged in a same direction.
 8. The semiconductor structureaccording to claim 7, wherein the plurality of capacitor banks arearranged in parallel, and the first functional pad and the secondfunctional pad are both positioned between adjacent two of the pluralityof capacitor banks.
 9. The semiconductor structure according to claim 1,wherein an area of the first electrode plate is greater than or equal toan area of the first dummy pad.
 10. The semiconductor structureaccording to claim 1, wherein an area of the first dummy pad is greaterthan or equal to an area of the second dummy pad.
 11. The semiconductorstructure according to claim 1, wherein an area of the first dummy padis equal to an area of the first functional pad, and an area of thesecond dummy pad is equal to an area of the second functional pad. 12.The semiconductor structure according to claim 11, wherein the area ofthe first dummy pad is 0.01 um² to 100 um², the area of the second dummypad being 0.01 um² to 100 um², the area of the first functional padbeing 0.01 um² to 100 um², and the area of the second functional padbeing 0.01 um² to 100 um².
 13. The semiconductor structure according toclaim 1, wherein the surface of the second wafer further has a secondelectrode plate, a second dielectric layer and a second connectionlayer; the second electrode plate, the second dielectric layer and thesecond dummy pad are sequentially stacked on the surface of the secondwafer; and the second connection layer is connected to the secondelectrode plate and is spaced apart from the second dummy pad; thesurface of the first wafer further has a first connection layer, thefirst connection layer being further connected to the first electrodeplate and being spaced apart from the first dummy pad; and the firstconnection layer is connected to the second connection layer, both thefirst connection layer and the second connection layer extending in adirection perpendicular to an upper surface of the first wafer.
 14. Amethod for fabricating a semiconductor structure, comprising: providinga first wafer; forming, on a surface of the first wafer, a firstelectrode plate, a first dielectric layer and a first dummy pad stackedin sequence to constitute a capacitor; and forming a first functionalpad on the surface of the first wafer, the first functional pad and thefirst dummy pad being arranged on a same layer; providing a secondwafer; forming, on a surface of the second wafer, a second dummy pad anda second functional pad arranged on a same layer; and bonding the firstdummy pad to the second dummy pad, and bonding the first functional padto the second functional pad, such that the first wafer is bonded to thesecond wafer.
 15. The method for fabricating the semiconductor structureaccording to claim 14, wherein before forming the first electrode plate,the method further comprises: forming a first wiring layer in the firstwafer; forming, in the first wafer, a first conductive plug and a secondconductive plug connected to the first wiring layer; forming thecapacitor comprises: removing the first wafer by a part of thickness toform a groove in the first wafer, the groove being positioned directlyabove the first conductive plug; forming a first electrode plate in thegroove, the first electrode plate being connected to the firstconductive plug; forming a first dielectric layer in the groove, thefirst dielectric layer further covering the first electrode plate;forming a first surface dielectric layer on the surface of the firstwafer; and forming a first dummy pad and a first functional pad in thefirst surface dielectric layer, the first dummy pad being positioneddirectly above the first electrode plate, and the first functional padbeing connected to the second conductive plug.